Priv.-Doz. Dr. Amir Moradi
- Privat-Dozent/in - Lehrstuhl Embedded Security
Lehrstuhl für Eingebette Sicherheit
Fakultät für Elektrotechnik und Informationstechnik
- ID 2/619
- (+49)(0)234 / 32 - 27219
- firstname.lastname@example.org PGP Schlüssel
- Since 5/2016: Academic Councilor (Akademischer Rat)Embedded Security, Ruhr-Universität Bochum, Germany
- Since 10/2015: Faculty Member (Privatdozent)Faculty of Electrical Engineering and Information Sciences, Ruhr-Universität Bochum, Germany
- 2009-2016: post-doctoral researcherEmbedded Security, Ruhr-Universität Bochum, Germany
- 2008: PhD in Computer EngineeringSharif University of Technology, Tehran, Iran
- 2007-2008: visiting PhD studentEmbedded Security, Ruhr-Universität Bochum, Germany
- 2004: MSc in Computer EngineeringSharif University of Technology, Tehran, Iran
- 2001: BSc in Computer EngineeringShahid Beheshti University, Tehran, Iran
- Side-Channel Cryptanalysis
- Efficient Implementation of Cryptographic Algorithms
- Applied Cryptography
- Co-author of the Best Student-Paper Award at International Conference on Applied Cryptography and Network Security - ACNS 2014.
- Best Paper Award at International Workshop on Constructive Side-Channel Analysis and Secure Design - COSADE 2015.
- Co-author of the Best Student-Paper Award at IEEE International Symposium on Hardware Oriented Security and Trust - HOST 2016.
- since Summer 2011, Physical Attacks and Countermeasures, Dep. of Elect. Engineering and Info. Sciences, Ruhr University Bochum, 141028.
- since Winter 2015/16, Cryptography on Hardware-based Platforms, Dep. of Elect. Engineering and Info. Sciences, Ruhr University Bochum, 141031.
- since Winter 2010/11, Side-Channel Attacks (Lab Course), Dep. of Elect. Engineering and Info. Sciences, Ruhr University Bochum, 142023.
- Winter 2009/10 - Winter 2014/15, Embedded Smartcard Microcontrollers (Lab Course), Dep. of Elect. Engineering and Info. Sciences, Ruhr University Bochum, 142020.
- Fall 2006, Spring 2007, Logical Circuits, Department of Computer Engineering, Sharif University of Technology, CE40212.
- Spring 2006, Summer 2006, Digital Electronics Lab, Department of Computer Engineering, Sharif University of Technology, CE40307.
- Summer 2001, Logical Circuits Lab, Department of Computer Engineering, Sharif University of Technology, CE40206.
Program Committee/Editorial Board member of
- Smart Card Research and Advanced Application Conference (CARDIS 2011, CARDIS 2015, CARDIS 2016).
- International Conference on Information Security and Cryptology (INSCRYPT 2012).
- Constructive Side-Channel Analysis and Secure Design Workshop (COSADE 2013, COSADE 2014, COSADE 2015, COSADE 2016, COSADE 2017).
- International Workshop on Lightweight Cryptography for Security & Privacy (LightSec 2014, LightSec 2016).
- International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014, ReConfig 2015).
- International Workshop on Fast Software Encryption (FSE 2015, FSE 2016).
- Workshop on Cryptographic Hardware and Embedded Systems (CHES 2015, CHES 2016, CHES 2017).
- Workshop on Secure Hardware and Security Evaluation (TRUDEVICE 2015).
- International Workshop on the Arithmetic of Finite Fields (WAIFI 2016).
- Euromicro Conference on Digital System Design (DSD 2016, DSD 2017) special session on Architectures and Hardware for Security Applications.
- International Conference on the Theory and Application of Cryptology and Information Security, (ASIACRYPT 2016, ASIACRYPT 2017).
- International Conference on Cryptology in India, (INDOCRYPT 2016).
- Design, Automation & Test in Europe Conference & Exhibition A5 Secure Systems (DATE 2017).
- International Journal of Applied Cryptography (IJACT).
- Smart Card Research and Advanced Application Conference (PC co-Chair) (CARDIS 2014).
- Smart Card Research and Advanced Application Conference (General co-Chair) (CARDIS 2015).
- International Workshop on Lightweight Cryptography for Security & Privacy (General and PC co-Chair) (LightSec 2015).
- Statistical Tools Flavor Side-Channel Collision Attacks EUROCRYPT 2012, April 17, Cambridge, UK.
- Breaking the Bitstream Decryption of FPGAs invited talk at ECRYPT II Summer School: Challenges in Security Engineering, 2012, September 5, Bochum, Germany.
- How Far Should Theory Be from Practice? Evaluation of a Countermeasure CHES 2012, September 10, Leuven, Belgium.
- On the Simplicity of Converting Leakages from Multivariate to Univariate CHES 2013, August 21, Santa Barbara, US.
- Altera vs. Xilinx which one keeps your design hidden? rump session CHES 2013, August 22, Santa Barbara, US.
- Side-Channel Countermeasures for Hardware: is There a Light at the End of the Tunnel? invited talk at Worcester Polytechnic Institute, 2013, September 11, Worcester, US.
- Evaluation of Side-Channel Leakages through Statistical Moments invited talk at Bosch GmbH, 2014, March 13, Stuttgart, Germany.
- Side-Channel Leakage through Static Power Should We Care about in Practice? invited talk at NXP Semiconductors, 2014, April 22, Hamburg, Germany (+ CHES 2014, September 26, Busan, South Korea).
- Early Propagation and Imbalanced Routing, How to Diminish in FPGAs CHES 2014, September 26, Busan, South Korea.
- Physical Attacks, extracting the secrets from cryptographic devices invited talk at Bauhaus-Universität Weimar, 2015, January 22, Weimar, Germany.
- Side-Channel Security Analysis of Ultra-Low-Power FRAM-based MCUs COSADE 2015, April 14, Berlin, Germany.
- Hiding Higher-Order Leakages in Hardware invited talk at TI day, KU Leuven, Belgium.
- Leakage Assessment Methodology - a clear roadmap for side-channel evaluations invited talk at Sharif University of Technology, 2015, August 29, Tehran, Iran.
- Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series COSADE 2016, April 14, Graz, Austria.
- Masking as a Side-Channel Countermeasure in Hardware invited tutorial at ISCISC 2016, September 6, Tehran, Iran.
- Moments-Correlating DPA CCS 2016 Workshops (TIs), October 24, Vienna, Austria.
- Side-Channel Analysis Protection and Low-Latency in Action - case study of PRINCE and Midori ASIACRYPT 2016, December 07, Hanio, Vietnam.
- NaSCA- Nano-Scale Side-Channel Analysis: Physical Security for Next-Generation CMOS ICs (DFG 2016-2019)
- 141031: Kryptographie auf hardwarebasierten Plattformen
- 142023: Master-Praktikum Seitenkanalangriffe
- 141028: Physical Attacks and Countermeasures
Bridging the Gap: Advanced Tools for Side-Channel Leakage Estimation beyond Gaussian Templates and Histograms
Assessment of Hiding the Higher-Order Leakages in Hardware - what are the achievements versus overheads?
A Hardware-based Countermeasure to Reduce Side-Channel Leakage - Design, Implementation, and Evaluation
Side-Channel Protection by Randomizing Look-Up Tables on Reconfigurable Hardware - Pitfalls of Memory Primitives
Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs
On the Simplicity of Converting Leakages from Multivariate to Univariate - Case Study of a Glitch-Resistant Masking Scheme
On the Vulnerability of FPGA Bitstream Encryption against Power Analysis Attacks – Extracting Keys from Xilinx Virtex-II FPGAs