Design Space Exploration of PRESENT Implementations for FPGAs

Mohamad Sbeiti, Michael Silbermann, Dipl.-Kfm. Axel Poschmann, Chris­tof Paar

Proceedings of the 5th Southern Programmable Logic Conference -- SPL'09, Sao Carlos, Brazil, April 1 - 3, 2009.


In this paper we investigate the performance of the block cipher PRESENT on FPGAs. We provide implementation results of an efficiency (i.e. throughput per slice) optimized design and compare them with other block ciphers. Though PRESENT was originally designed with a minimal hardware footprint in mind, our results also highlight that PRESENT is well suited for high-speed and high-throughput applications. Especially its hardware efficiency, i.e. the throughput per slice, is noteworthy.

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Tags: FPGA