SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA

Maik Ender, Alexander Wild, Amir Moradi

8th In­ter­na­tio­nal Work­shop on Con­struc­tive Si­de-Chan­nel Ana­ly­sis and Se­cu­re De­sign, COSA­DE 2017, Paris, France, April 13-14, 2017.


Abstract

Side-channel analysis attacks, particularly power analysis attacks, have become one of the major threats, that hardware designers have to deal with. To defeat them, the majority of the known concepts are based on either masking, hiding, or rekeying (or a combination of them). This work deals with a hiding scheme, more precisely a power-equalization technique which is ideally supposed to make the amount of power consumption of the device independent of its processed data. We propose and practically evaluate a novel construction dedicated to Xilinx FPGAs, which rules out the state of the art with respect to the achieved security level and the resource overhead.

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Tags: hardware implementations, Implementation attacks, Side-channel countermeasures