Side-Channel Leakage through Static Power – Should We Care about in Practice?

Amir Moradi

Work­shop on Cryp­to­gra­phic Hard­ware and Em­bed­ded Sys­tems, CHES 2014, Busan, Korea, September 23 - 26, 2014.


Abstract

By shrinking the technology static power consumption of CMOS circuits is becoming a major concern. In this paper, we present the first practical results of exploiting static power consumption of FPGA-based cryptographic devices in order to mount a key-recovery side-channel attack. The experiments represented here are based on three Xilinx FPGAs built on 65nm, 45nm, and 28nm process technologies. By means of a sophisticated measurement setup and methodology we demonstrate an exploitable information leakage through static power of the underlying FPGAs. The current work highlights the feasibility of side-channel analysis attacks by static power that have been known for years but have not been performed and investigated in practice yet. This is a starting point for further research investigations, and may have a significant impact on the efficiency of DPA countermeasures in the near future.

[DOI] [pdf]

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