Efficient Hardware Architectures for Modular Multiplication on FPGAs

D. Amanor, V. Bunimov, Chris­tof Paar, Jan Pelzl

International Conference on Field Programmable Logic, Reconfigurable Computing and Applications, FPL 2005, Tampere, Finland, August 24-28, 2005.


Abstract

The computational fundament ofmost public-key cryptosystems is the modularmultiplication. Improving the ef?ciency of the modular multiplication is directly associated with the ef?ciency of the whole cryptosystem. This paper presents an implementation and comparison of three recently proposed, highly ef?cient architectures for modular multiplication on FPGAs: interleaved modular multiplication and two variants of the Montgomery modular multiplication. This (?rst) hardware implementation of these designs shows their relative performance regarding area and speed.

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Tags: cryptography, FPGA, Hardware, RSA