An FPGA-Based Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists

A. Elbirt, W. Yip, B. Chetwynd, Chris­tof Paar

IEEE Transactions on VLSI, vol. 9, no. 4, pp. 545, August, 2001.


Abstract

The technical analysis used in determining which of the potential Advanced Encryption Standard candidates was selected as the Advanced Encryption Algorithm includes ef-

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ciency testing of both hardware and software implementations

of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the signi cance of FPGA implementations of the Advanced Encryption Standard candidate algorithms. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high throughput implementations, which are required to support security for current and future high bandwidth applications. Finally, the implementations of each algorithm will be compared in an e ort to determine the most suitable candidate for hardware implementation within commercially available FPGAs.

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Tags: ieee, VLSI