A Pipelined Camellia Architecture for Compact Hardware Implementation

Elif Bilge Kavun, Tolga Yalcin

In Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP’10), pages 305 - 308, IEEE, Rennes, France, July 7-9, 2010


In this paper, we present a compact and fast pipelined implementation of the block cipher Camellia for 128-bit data and 128-bit key lengths. The implementation is suitable for both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms, and is targeted for low area and low power applications. To obtain a compact design, pipelining principles are exploited and platform specific optimizations are made. The design requires only 321 slices with a throughput of 32.96 Mbps based on Xilinx Spartan-S XC3S50-5 chip and 4.31K gates with a throughput of 81 Mbps based on 0.13-um CMOS standard cell library.


Tags: ASIC, block cipher, Camellia, cryptographic hardware, cryptography, efficient implementation, FPGA